The increase of the density of electronic components (diode, transistors, resistors, capacitors . . . ), that is, the number of components per surface area unit, in electronic circuits often comes up against the limited accuracy of manufacturing methods, particularly photolithography. This issue is all the more present for an electric component which comprises a plurality of successively-manufactured parts requiring an accurate positioning with respect to one another, for example, to avoid short-circuits. Further, the difficulty is all the greater when a plurality of connection levels are present in an electronic component, as is especially the case in an “island”-type dipole, for example, a photodiode (commonly called “mesa” photodiode), which requires applying a potential difference between the top and the foot of the island in order to operate.
Such issues are illustrated in FIGS. 1 and 2 in the specific case of a display and an array detector based on photodiodes.
Referring to FIGS. 1 and 2, conventionally, to form a matrix display (respectively detector) 20, a photodiode array 10 is formed in a first electronic emission (respectively detection) component 22 and current injection circuits 14 (respectively current collection circuits 18) are formed in a second electronic control (respectively read) component 24. The two components 22, 24 are manufactured independently from each other, and are then hybridized with each other by means of a so-called “flip-chip” technique. The hybridization enables to electrically connect electrodes 12 of photodiodes 10 with their respective injection circuits 14 (respectively collection circuits 18), by means of metal interconnects 24, which are usually also provided to secure components 22, 24 to each other. Electrodes 16 of photodiodes 10 are for example connected to a same electric potential by means of various techniques. According to a first technique, first component 22 comprises, inside thereof or on its surface 26 intended to be connected with component 24, a conductive or heavily-doped layer in contact with all the electrodes 16 of photodiodes 10. This technique is however crippling for arrays of photodiodes of large dimensions due to the series electric resistance implied by said layer.
Thereby, electrodes 12, 16 of photodiodes 10 are manufactured to be accessible from surface 26 of component 22 for their electric connection. At the same time, since a photodiode is essentially made of volumes of different materials stacked and/or aligned with one another, the manufacturing of photodiodes 10 advantageously uses etch techniques for automatically aligning a maximum number of components of the photodiodes. Such a manufacturing is illustrated in FIG. 2, which is a simplified cross-section view of a mesa-type photodiode 10 in a simplified PN junction form.
More specifically referring to FIG. 2, to manufacture photodiode 10, a volume of semiconductor material, for example, P-type doped, 30, is formed on a layer 32 of semiconductor material, for example, N-type doped, 32, to form a PN junction. An island of P-type semiconductor material 34 is then separated by depositing by photolithography an etch mask on P volume 30, for example, a SiO2 mask deposited by a plasma-enhanced vapor phase deposition technique (“PECVD”), and by then applying an etching to form a trench 36 around volume 34 to reach N-type semiconductor material (see above) 32. For example, the etching is an inductively coupled plasma reactive ion etching (“RIE-ICP”). The etching is also applied to form a trench 38 of same height to isolate a P island 40 close to P island 34. A passivation layer 42, for example, made of SiN, is then deposited all over the surface of P islands 34, 40 and the surface of trenches 36, 38, for example, by means of a PECVD. Passivation layer 42, although it is optional, is considered as almost unavoidable. Not only does it correct the surface defects of P island 34, which defects are an important cause of unwanted recombinations of the charge carriers, but also does layer 42 enable to electrically isolate different elements of photodiode 10, and thus provides a protection against possible short-circuits during the subsequent deposition of the metal forming the electrodes of photodiode 10. The method of manufacturing photodiode 10 carries on with the forming of openings 44, 46 in passivation layer 42, both on top of P island 34 and at the bottom of trench 36 individualizing it, for example, by means of a RIE. A metal layer is then deposited full plate and it then etched to expose a first metallization 48 at the top of P island 34 forming a first electrode 12 of photodiode 10 as well as a second metallization 50, isolated from metallization 48, formed at the bottom of trench 36 and forming a second electrode 16 of photodiode 10. Such a structure thus allows a contacting, for example, by solder bumps 52 of component 24, of anode 12 and of cathode 16 substantially at the same level, which eases the hybridization with component 24. This structure is however highly area-consuming and the pitch of the array of photodiodes is substantially doubled, which thus limits the photodiode integration density.
To increase the integration density, it would thus be possible not to provide a contacting area for the cathode at the same level as the anode. P island 40 is thus suppressed and the contacting area of cathode 16 is formed directly at the bottom of trench 36. This type of structure is conventional. However, as described in document “A Novel Blu-free Full-Color LED projector Using LED on Silicon Micro-Displays” of Z. J. Liu et al., IEEE Photonics Technology Letters, vol. 25, No. 3, December 2013, this assumes providing connections 52 of different heights on component 24, which is particularly complex when a high-quality hybridization is desired. Further, when the cathode contacting area is formed directly at the bottom of trench 36, the access thereto becomes very difficult if the trench diameter is small. This thus requires at best very accurate alignment tools, which are thus very expensive. At worst, it is impossible to go below a given array pitch.
It may similarly be envisaged to decrease the width of trench 36 to decrease the pitch of the photodiode array. However, a problem is then posed in the forming of opening 46 providing access to the N layer for the cathode design. Further, by decreasing the width of trench 36, specific precautions should be taken so that metallization 50 does not overlap metallization 44. It is thus desirable to use manufacturing techniques far beyond their accuracy to guarantee the desired positioning of the photodiode elements with respect to one another. It can thus be noted that in the state of the art, such as for example described in document “360 PPI Flip-Chip Mounted Active Matrix Addressable Light Emitting Diode on Silicon (LEDoS) Micro-Display”, of Z. J. Liu, Journal of Display Technology, vol. 9, No. 8, August 2013, or also described in the following document, the pitch of the array is in the order of some ten micrometers.
Of course, what has just been discussed, although it has been described in relation with diodes, applies to any type of electronic component, particularly dipoles, as soon as two electrodes of this component respectively associated with two different levels are desired to be connected. For example, the above-described issue applies to an array of photoconductors, for example, formed of a N/N+ or P/P+ stack, to an array of capacitors, an array of bolometers, an array of Zener diodes, etc.